1. Technical Field
The present disclosure relates to processor systems for electronic devices, and particularly to a dual processor system and a method for using the same.
2. Description of Related Art
Many electronic devices use dual processor systems to improve data processing rates. Dual-ported random access memory (DPRAM) are often used in the dual processor systems for communication between the dual processors. For example, FIG. 3 shows one such dual processor system 300, which includes a first processor 40, a second processor 50, and a DPRAM 60. The DPRAM 60 includes a data area 61, a mailbox area 62, a first interrupt pin Int1, and a second interrupt pin Int2. The mailbox area 62 includes a first mailbox 621 and a second mailbox 622. The data area 61, the first mailbox area 621, and the second mailbox 622 are all electrically connected to both the first processor 40 and second processor 50. The first interrupt pin Int1 and the second interrupt pin Int2 are electrically connected to the first processor 40 and the second processor 50, respectively.
In use of the dual processor system 300, the first processor 40 and second processor 50 can communicate with each other through the DPRAM 60, thereby cooperating with each other to process data. For example, when the second processor 50 is used to share data processing work of the first processor 40, the first processor 40 stores the data to be processed by the second processor 50 in the data area 61. When the first processor 40 completes storing the data to be processed by the second processor 50, the first processor 40 writes first interrupt data to the second mailbox 622. Upon receiving the first interrupt data, the DPRAM 60 correspondingly generates a first information status (e.g., a predetermined low voltage level) on the second interrupt pin Int2. Upon detecting the first information status generated on the second interrupt pin Int2, the second processor 50 reads the first interrupt data stored in the second mailbox 622. When the second processor 50 has successfully read the first interrupt data in the second mailbox 622, the DPRAM 60 correspondingly generates a second information status (e.g., a predetermined high voltage level) on the second interrupt pin Int2. Upon detecting the second information status, the second processor 50 processes the data stored in the data area 61.
When the second processor 50 completes the processing work of the data stored in the data area 61, the second processor 50 writes second interrupt data to the first mailbox 621. Upon receiving the second interrupt data, the DPRAM 60 correspondingly generates a third information status (e.g., a voltage level having a predetermined voltage value) on the first interrupt pin Int1. Upon detecting the third information status, the first processor 50 reads the second interrupt data from the first mailbox 621, and identifies that the second processor 50 has already processed the data stored in the data area 61 according to the second interrupt data.
As above detailed, each cooperative data processing work of the first processor 40 and the second processor 50 needs to perform many data transmission operations. These data transmission operations may decrease data processing rate of the dual processor system 300, and occupy many system resources of electronic devices using the dual processor system 300.
Therefore, there is room for improvement within the art.